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INTEGRATED CIRCUITS
DATA SHEET
74LVC162373A; 74LVCH162373A 16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
Product specification Supersedes data of 1999 Aug 05 2004 Feb 05
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination 74LVC162373A; resistors; 5 V tolerant inputs/outputs; 3-state 74LVCH162373A
FEATURES * 5 V tolerant inputs/outputs for interfacing with 5 V logic * Wide supply voltage range from 1.2 to 3.6 V * CMOS low power consumption * MULTIBYTE flow-through standard pin-out architecture * Low inductance multiple power and ground pins for minimum noise and ground bounce * Direct interface with TTL levels * All data inputs have bushold (74LVCH162373A only) * High-impedance when VCC = 0 V * Complies with JEDEC standard no. 8-1A * ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V. * Specified from -40 to +85 C and -40 to +125 C. DESCRIPTION The 74LVC(H)162373A is a 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. One latch enable (pin nLE) input and one output enable (pin nOE) are provided for each octal. Inputs can be driven from either 3.3 or 5 V devices. In 3-state operation, outputs can handle 5 V. These features allow the use of these devices in a mixed 3.3 and 5 V environment. The 74LVC(H)162373A consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When pin nLE is HIGH, data at the corresponding data inputs (pins nDn) enter the latches. In this condition the latches are transparent, i.e., a latch output will change each time its corresponding data inputs changes. When pin nLE is LOW the latches store the information that was present at the data inputs a set-up time preceding the HIGH-to-LOW transition of pin nLE. When pin nOE is LOW, the contents of the eight latches are available at the outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the nOE input does not affect the state of the latches. The 74LVCH162373A bushold data inputs eliminates the need for external pull-up resistors to hold unused inputs. The 74LVC(H)162373A is designed with 30 series termination resistors in both high and low output stages to reduce line noise. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 C; tr = tf 2.5 ns SYMBOL tPHL/tPLH tPZH/tPZL tPHZ/tPLZ CI CPD PARAMETER propagation delay nDn to nQn propagation delay nLE to nQn CONDITIONS CL = 50 pF; VCC = 3.3 V CL = 50 pF; VCC = 3.3 V TYPICAL 3.3 3.5 4.0 3.4 5.0 VCC = 3.3 V; notes 1 and 2 outputs enabled outputs disabled Notes 1. CPD is used to determine the dynamic power dissipation (PD in W). PD = CPD x VCC2 x fi x N + (CL x VCC2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz; CL = output load capacitance in pF; 2004 Feb 05 2 26 19 pF pF ns ns ns ns pF UNIT
3-state output enable time nOE to nQn CL = 50 pF; VCC = 3.3 V 3-state output disable time nOE to nQn CL = 50 pF; VCC = 3.3 V input capacitance power dissipation per latch
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
VCC = supply voltage in Volts; N = total load switching outputs; (CL x VCC2 x fo) = sum of the outputs. 2. The condition is VI = GND to VCC. ORDERING INFORMATION TYPE NUMBER 74LVC162373ADGG 74LVCH162373ADGG 74LVC162373ADL 74LVCH162373ADL FUNCTION TABLE Per section of eight bits; note 1 INPUT OPERATING MODES nOE Enable and read register (transparent mode) Latch and read register Latch register and disable outputs L L L L H H Note 1. H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition; L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition; Z = high-impedance OFF-state. nLE H H L L L L nDn L H l h l h TEMPERATURE RANGE -40 to +125 C -40 to +125 C -40 to +125 C -40 to +125 C
74LVC162373A; 74LVCH162373A
PACKAGE PINS 48 48 48 48 PACKAGE TSSOP48 TSSOP48 SSOP48 SSOP48 MATERIAL plastic plastic plastic plastic CODE SOT362-1 SOT362-1 SOT370-1 SOT370-1
INTERNAL LATCH L H L H L H
OUTPUT nQn L H L H Z Z
2004 Feb 05
3
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
PINNING SYMBOL 1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2OE 2LE 2D7 2D6 2D5 2D4 2D3 2D2 2D1 2D0 1D7 1D6 1D5 1D4 1D3 1D2 PIN 1 2 3 4, 10, 15, 21, 28, 34, 39, 45 5 6 7, 18, 31, 42 8 9 11 12 13 14 16 17 19 20 22 23 24 25 26 27 29 30 32 33 35 36 37 38 40 41 43 44 DESCRIPTION output enable input (active LOW) data output data output ground (0 V) data output data output supply voltage data output data output data output data output data output data output data output data output data output data output data output data output output enable input (active LOW) latch enable input (active HIGH) data input data input data input data input data input data input data input data input data input data input data input data input data input data input
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1 2 3 4 5 6 7 8 9
74LVC162373A; 74LVCH162373A
DESCRIPTION data input data input latch enable input (active HIGH)
SYMBOL 1D1 1D0 1LE
PIN 46 47 48
48 1LE 47 1D0 46 1D1 45 GND 44 1D2 43 1D3 42 VCC 41 1D4 40 1D5 39 GND 38 1D6 37 1D7 36 2D0 35 2D1 34 GND 33 2D2 32 2D3 31 VCC 30 2D4 29 2D5 28 GND 27 2D6 26 2D7 25 2LE
001aaa336
GND 10 1Q6 11 1Q7 12 2Q0 13 2Q1 14 GND 15 2Q2 16 2Q3 17 VCC 18 2Q4 19 2Q5 20 GND 21 2Q6 22 2Q7 23 2OE 24
162373A
Fig.1 Pin configuration SSOP48 and TSSOP48.
2004 Feb 05
4
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
74LVC162373A; 74LVCH162373A
handbook, full pagewidth
1D0
D
Q
1Q0
2D0
D
Q
2Q0
LATCH 1 LE LE
LATCH 9 LE LE
1LE 1OE to 7 other channels
2LE 2OE to 7 other channels
MGU769
Fig.2 Logic diagram.
1
24
1OE 1LE
1 48 24 25 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26
1EN C3 2EN C4 3D 1 2 3 5 6 8 9 11 12 4D 2 13 14 16 17 19 20 22 23
mgu770
1OE 47 46 44 43 41 40 38 37 36 35 33 32 30 29 27 26 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 1LE 48
2OE 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2LE 25
mgu768
2OE 2 3 5 6 8 9 11 12 13 14 16 17 19 20 22 23 1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2LE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
Fig.3 Logic symbol.
Fig.4 Logic symbol (IEEE/IEC).
2004 Feb 05
5
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
74LVC162373A; 74LVCH162373A
handbook, halfpage
VCC
input
to internal circuit
MNA428
Fig.5 Bushold circuit.
RECOMMENDED OPERATING CONDITIONS SYMBOL VCC VI VO Tamb tr, tf PARAMETER supply voltage input voltage output voltage operating ambient temperature input rise and fall times output HIGH or LOW state output 3-state in free-air VCC = 1.2 to 2.7 V VCC = 2.7 to 3.6 V CONDITIONS for maximum speed performance for low-voltage applications MIN. 2.7 1.2 0 0 0 -40 0 0 MAX. 3.6 3.6 5.5 VCC 5.5 +125 20 10 UNIT V V V V V C ns/V ns/V
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V). SYMBOL VCC IIK VI IOK VO IO ICC, IGND Tstg Ptot Notes 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. Above 60 C the value of Ptot derates linearly with 5.5 mW/K. PARAMETER supply voltage input diode current input voltage output diode current output voltage output source or sink current VCC or GND current storage temperature power dissipation Tamb = -40 to +125 C; note 2 VI < 0 note 1 VO > VCC or VO < 0 output HIGH or LOW state; note 1 output 3-state; note 1 VO = 0 to VCC CONDITIONS - -0.5 - -0.5 -0.5 - - -65 - MIN. -0.5 MAX. +6.5 -50 +6.5 50 +6.5 50 100 +150 500 UNIT V mA V mA V mA mA C mW
VCC + 0.5 V
2004 Feb 05
6
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
DC CHARACTERISTICS At recommended operating conditions; voltages are referenced to GND (ground = 0 V). TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +85 C; note 1 VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -6 mA IO = -12 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 6 mA IO = 12 mA ILI IOZ input leakage current 3-state output OFF-state current VI = 5.5 V or GND; note 3 VI = VIH or VIL; VO = 5.5 V or GND; note 3 VI = VCC or GND; IO = 0 VI = VCC - 0.6 V; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 - - - - - 2.7 to 3.6 2.7 3.0 VCC - 0.2 VCC - 0.5 VCC - 0.8 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 - - VCC (V) MIN.
74LVC162373A; 74LVCH162373A
TYP.
MAX.
UNIT
- - - - VCC(2) - - GND(2) - - 0.1 0.1
- - GND 0.8 - - - 0.20 0.40 0.55 5 5
V V V V V V V V V V A A
Ioff ICC ICC
power-off leakage current VI or VO = 5.5 V quiescent supply current additional quiescent supply current per input pin bushold LOW sustaining current bushold HIGH sustaining current bushold LOW overdrive current bushold HIGH overdrive current
0 3.6 2.7 to 3.6
- - -
0.1 0.1 5(2)
10 20 500
A A A
IBHL IBHH IBHLO IBHHO
VI = 0.8 V; notes 4 and 5 3.0 VI = 2.0 V; notes 4 and 5 3.0 notes 4 and 6 notes 4 and 6 3.6 3.6
75 -75 500 -500
- - - -
- - - -
A A A A
2004 Feb 05
7
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
TEST CONDITIONS SYMBOL PARAMETER OTHER Tamb = -40 to +125 C VIH VIL VOH HIGH-level input voltage LOW-level input voltage HIGH-level output voltage VI = VIH or VIL IO = -100 A IO = -6 mA IO = -12 mA VOL LOW-level output voltage VI = VIH or VIL IO = 100 A IO = 6 mA IO = 12 mA ILI IOZ input leakage current 3-state output OFF-state current VI = 5.5 V or GND; note 3 VI = VIH or VIL; VO = 5.5 V or GND; note 3 VI = VCC or GND; IO = 0 VI = VCC - 0.6 V; IO = 0 2.7 to 3.6 2.7 3.0 3.6 3.6 - - - - - 2.7 to 3.6 2.7 3.0 VCC - 0.3 VCC - 1 1.2 2.7 to 3.6 1.2 2.7 to 3.6 VCC 2.0 - - VCC (V) MIN.
74LVC162373A; 74LVCH162373A
TYP.
MAX.
UNIT
- - - - - - - - - - -
- - GND 0.8 - - - 0.3 0.6 0.8 20 20
V V V V V V V V V V A A
VCC - 0.65 -
Ioff ICC ICC
power off leakage current VI or VO = 5.5 V quiescent supply current additional quiescent supply current per input pin bushold LOW sustaining current bushold HIGH sustaining current bushold LOW overdrive current bushold HIGH overdrive current
0 3.6 2.7 to 3.6
- - -
- - -
20 80 5000
A A A
IBHL IBHH IBHLO IBHHO Notes
VI = 0.8 V; notes 4 and 5 3.0 VI = 2.0 V; notes 4 and 5 3.0 notes 4 and 6 notes 4 and 6 3.6 3.6
60 -60 500 -500
- - - -
- - - -
A A A A
1. All typical values are measured at Tamb = 25 C. 2. Measured at VCC = 3.3 V. 3. For bushold parts, the bushold circuit is switched off when VI > VCC allowing 5.5 V on the input pin. 4. Valid for data inputs of bushold parts (LVCH162373A) only. For data inputs only; control inputs do not have a bushold circuit. 5. The specified sustaining current at the data inputs holds the input below the specified VI level. 6. The specified overdrive current at the data input forces the data input to the opposite logic input state.
2004 Feb 05
8
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
AC CHARACTERISTICS GND = 0 V; tr = tf 2.5 ns; CL = 50 pF; RL = 500 . CONDITIONS SYMBOL PARAMETER WAVEFORMS Tamb = -40 to +85 C; note1 tPHL/tPLH propagation delay nDn to nQn see Fig 6 and 10 1.2 2.7 3.0 to 3.6 propagation delay nLE to nQn see Fig 7 and 10 1.2 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time nOE to nQn see Fig 8 and 10 1.2 2.7 3.0 to 3.6 tPHZ/tPLZ 3-state output disable time nOE to nQn see Fig 8 and 10 1.2 2.7 3.0 to 3.6 tW nLE pulse width HIGH see Fig 7 1.2 2.7 3.0 to 3.6 tsu set-up time nDn to nLE see Fig 9 1.2 2.7 3.0 to 3.6 th hold time nDn to nLE see Fig 9 1.2 2.7 3.0 to 3.6 tsk(0) skew note 3 3.0 to 3.6 - 1.5 1.0 - 1.5 1.5 - 1.5 1.0 - 1.5 1.5 - 3.0 3.0 - 2.0 2.0 - 0.9 0.9 - VCC (V)
74LVC162373A; 74LVCH162373A
MIN.
TYP.
MAX.
UNIT
12 - 3.3(2) 14 - 3.5(2) 18 - 4.0(2) 11 - 3.4(2) - - 2.0(2) - - 1.0(2) - - -1.0(2) -
- 6.7 5.9 - 7.0 6.1 - 7.5 6.1 - 4.8 4.6 - - - - - - - - - 1.0
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
2004 Feb 05
9
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
CONDITIONS SYMBOL Tamb = -40 to +125 C tPHL/tPLH propagation delay nDn to nQn see Fig 6 and 10 1.2 2.7 3.0 to 3.6 propagation delay nLE to nQn see Fig 7 and 10 1.2 2.7 3.0 to 3.6 tPZH/tPZL 3-state output enable time nOE to nQn see Fig 8 and 10 1.2 2.7 3.0 to 3.6 tPHZ/tPLZ 3-state output disable time nOE to nQn see Fig 8 and 10 1.2 2.7 3.0 to 3.6 tW nLE pulse width HIGH see Fig 7 1.2 2.7 3.0 to 3.6 tsu set-up time nDn to nLE see Fig 9 1.2 2.7 3.0 to 3.6 th hold time nDn to nLE see Fig 9 1.2 2.7 3.0 to 3.6 tsk(0) Notes 1. All typical values are measured at Tamb = 25 C. 2. Measured at VCC = 3.3 V. skew note 3 3.0 to 3.6 - 1.5 1.0 - 1.5 1.5 - 1.5 1.0 - 1.5 1.5 - 3.0 3.0 - 2.0 2.0 - 0.9 0.9 - PARAMETER WAVEFORMS VCC (V)
74LVC162373A; 74LVCH162373A
MIN.
TYP.
MAX.
UNIT
- - - - - - - - - - - - - - - - - - - - - -
- 8.5 7.5 - 9.0 8.0 - 9.5 8.0 - 6.0 6.0 - - - - - - - - - 1.5
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
3. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
2004 Feb 05
10
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
AC WAVEFORMS
74LVC162373A; 74LVCH162373A
VI nDn input GND t PHL VOH nQn output VOL VM
mna429
VM
t PLH
INPUT VCC 1.2 V 2.7 V 3.0 to 3.6 V VM 0.5 x VCC 1.5 V 1.5 V VCC 2.7 V 2.7 V VI tr = tf 2.5 ns 2.5 ns 2.5 ns
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.6 Input (nDn) to output (nQn) propagation delays.
VI nLE input GND tW t PHL VOH nQn output VOL VM
mna430
VM
t PLH
INPUT VCC 1.2 V 2.7 V 3.0 to 3.6 V VM 0.5 x VCC 1.5 V 1.5 V VCC 2.7 V 2.7 V VI tr = tf 2.5 ns 2.5 ns 2.5 ns
VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.7 Latch enable input (nLE) pulse width, and the latch enable input to output (nQn) propagation delays.
2004 Feb 05
11
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
74LVC162373A; 74LVCH162373A
VI nOE input GND t PLZ VCC nQn output LOW-to-OFF OFF-to-LOW VOL t PHZ VOH nQn output HIGH-to-OFF OFF-to-HIGH GND outputs enabled outputs disabled outputs enabled
mna432
VM
t PZL
VM VX t PZH VY VM
INPUT VCC 1.2 V 2.7 V 3.0 to 3.6 V VM 0.5 x VCC 1.5 V 1.5 V VCC 2.7 V 2.7 V VI tr = tf 2.5 ns 2.5 ns 2.5 ns
VX = VOL + 0.3 V at VCC 2.7 V. VX = VOL + 0.1VCC at VCC < 2.7 V. VY = VOH - 0.3 V at VCC 2.7 V. VY = VOH - 0.1VCC at VCC < 2.7 V. VOL and VOH are the typical output voltage drop that occur with the output load.
Fig.8 3-state enable and disable times.
VI nDn input GND th t su VI nLE input GND VM
mna431
VM
th t su
INPUT VCC 1.2 V 2.7 V 3.0 to 3.6 V VM 0.5 x VCC 1.5 V 1.5 V VCC 2.7 V 2.7 V VI tr = tf 2.5 ns 2.5 ns 2.5 ns
The shaded areas indicate when the input is permitted to change for predictable performance.
Fig.9 Data set-up and hold times for the nDn input to the nLE input.
2004 Feb 05
12
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
74LVC162373A; 74LVCH162373A
handbook, full pagewidth
VEXT VCC PULSE GENERATOR VI D.U.T. RT CL RL VO RL
MNA616
VCC 1.2 V 2.7 V 3.0 to 3.6 V Note
VI VCC 2.7 V 2.7 V
CL 50 pF 50 pF 50 pF
RL 500 (1) 500 500
VEXT tPLH/tPHL tPZH/tPHZ open open open GND GND GND tPZL/tPLZ 2 x VCC 2 x VCC 2 x VCC
1. The circuit performs better when RL = 1000 .
Definitions for test circuit: RL = Load resistor. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
Fig.10 Load circuitry for switching times.
2004 Feb 05
13
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
PACKAGE OUTLINES
SSOP48: plastic shrink small outline package; 48 leads; body width 7.5 mm
74LVC162373A; 74LVCH162373A
SOT370-1
D
E
A X
c y HE vM A
Z 48 25
Q A2 A1 (A 3) Lp 1 bp 24 wM L detail X A
pin 1 index
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2.8 A1 0.4 0.2 A2 2.35 2.20 A3 0.25 bp 0.3 0.2 c 0.22 0.13 D (1) 16.00 15.75 E (1) 7.6 7.4 e 0.635 HE 10.4 10.1 L 1.4 Lp 1.0 0.6 Q 1.2 1.0 v 0.25 w 0.18 y 0.1 Z (1) 0.85 0.40 8 o 0
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT370-1 REFERENCES IEC JEDEC MO-118 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
2004 Feb 05
14
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
74LVC162373A; 74LVCH162373A
TSSOP48: plastic thin shrink small outline package; 48 leads; body width 6.1 mm
SOT362-1
D
E
A X
c y HE vMA
Z
48
25
Q A2 A1 pin 1 index Lp L (A 3) A
1
e bp
24
wM
detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions). UNIT mm Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT362-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION A max. 1.2 A1 0.15 0.05 A2 1.05 0.85 A3 0.25 bp 0.28 0.17 c 0.2 0.1 D (1) 12.6 12.4 E (2) 6.2 6.0 e 0.5 HE 8.3 7.9 L 1 Lp 0.8 0.4 Q 0.50 0.35 v 0.25 w 0.08 y 0.1 Z 0.8 0.4 8o o 0
ISSUE DATE 99-12-27 03-02-19
2004 Feb 05
15
Philips Semiconductors
Product specification
16-bit D-type transparent latch; 30 series termination resistors; 5 V tolerant inputs/outputs; 3-state
DATA SHEET STATUS LEVEL I DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2)(3) Development DEFINITION
74LVC162373A; 74LVCH162373A
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN).
II
Preliminary data Qualification
III
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 3. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes in the products including circuits, standard cells, and/or software described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2004 Feb 05
16
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2004
SCA76
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
R20/02/pp17
Date of release: 2004
Feb 05
Document order number:
9397 750 12674

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